4. Cache Organization and Coherency

4.5 Relationship Between Cached and Uncached Operations


Uncached and uncached accelerated load and store instructions are executed in order, and non-speculatively. Such accesses are buffered in the uncached buffer by the processor until they can be issued to the System interface.

All uncached and uncached accelerated accesses retain program order within the uncached buffer. The processor continues issuing cached accesses while uncached accesses are queued in the uncached buffer.


NOTE: Cached accesses do not probe the uncached buffer for conflicts.


Buffered uncached stores prevent a SYNC instruction from graduating. However buffered uncached accelerated stores do not prevent a SYNC instruction from graduating. The processor continues issuing cached accesses speculatively and out of order beyond a SYNC instruction that is waiting to graduate.

An uncached load may be used to guarantee that the uncached buffer is flushed of all uncached and uncached accelerated accesses.

A SYNC instruction and the SysGblPerf* signal may be used to guarantee that all cache accesses and uncached stores have been globally performed as described in Chapter 6, the section titled "SysGblPerf* Signal."

An uncached load followed by a SYNC instruction may be used to guarantee that all cache accesses, uncached accesses, and uncached accelerated accesses have been globally performed.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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