4. Cache Organization and Coherency
All uncached and uncached accelerated accesses retain program order within the uncached buffer. The processor continues issuing cached accesses while uncached accesses are queued in the uncached buffer.
An uncached load may be used to guarantee that the uncached buffer is flushed of all uncached and uncached accelerated accesses.
A SYNC instruction and the SysGblPerf* signal may be used to guarantee that all cache accesses and uncached stores have been globally performed as described in Chapter 6, the section titled "SysGblPerf* Signal."
An uncached load followed by a SYNC instruction may be used to guarantee that all cache accesses, uncached accesses, and uncached accelerated accesses have been globally performed.